The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7567114 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 28, 2009

Filed:

Oct. 23, 2006
Applicant:

Yasushi Matsubara, Tokyo, JP;

Inventor:

Yasushi Matsubara, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01H 37/76 (2006.01); H01H 85/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device employs two electric fuses () connected in parallel to each other. First terminals of the electric fuses () are connected to a junction of first and second P-channel transistors (), which are connected in series between a high potential application line () and a ground, and connected to a third P-channel transistor (). Second terminals of the electric fuses () are connected to a low potential application line (). When an extra-high voltage is applied between the first and second terminals of the electric fuses (), a breakdown connection is produced in at least one of the electric fuses (). Thus, 1-bit information is written into the semiconductor device.


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Matsubara, Yasushi. (2009). Semiconductor device having two fuses in parallel (U.S. Patent No. 7567114). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7567114

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