The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2009
Filed:
Apr. 05, 2006
Mihaela Balseanu, Sunnyvale, CA (US);
Jia Lee, San Jose, CA (US);
Mei-yee Shek, Mountain View, CA (US);
Amir Al-bayati, San Jose, CA (US);
Li-qun Xia, Santa Clara, CA (US);
Hichem M'saad, Santa Clara, CA (US);
Mihaela Balseanu, Sunnyvale, CA (US);
Jia Lee, San Jose, CA (US);
Mei-Yee Shek, Mountain View, CA (US);
Amir Al-Bayati, San Jose, CA (US);
Li-Qun Xia, Santa Clara, CA (US);
Hichem M'Saad, Santa Clara, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.