The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2009
Filed:
Nov. 24, 2004
Rama Divakaruni, Ossing, NY (US);
Louis C. Hsu, Fishkill, NY (US);
Rajiv V. Joshi, Yorktown Heights, NY (US);
Carl J. Radens, LaGrangeville, NY (US);
Rama Divakaruni, Ossing, NY (US);
Louis C. Hsu, Fishkill, NY (US);
Rajiv V. Joshi, Yorktown Heights, NY (US);
Carl J. Radens, LaGrangeville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.