The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2009

Filed:

Nov. 30, 2006
Applicants:

Leonard Forbes, Corvallis, OR (US);

Joseph E. Geusic, Berkeley Heights, NJ (US);

Inventors:

Leonard Forbes, Corvallis, OR (US);

Joseph E. Geusic, Berkeley Heights, NJ (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

One aspect of this disclosure relates to a semiconductor structure, comprising a gettering region proximate to a device region in a semiconductor wafer. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids through a surface transformation process. Each of the voids has an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region. The structure includes a transistor formed using the device region. The transistor includes a gate dielectric over the device region, a gate over the gate dielectric, and a first diffusion region and a second diffusion region formed in the device region. The first and second diffusion regions are separated by a channel region formed in the device region between the gate and the proximity gettering region.


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