Compare circuit for a content addressable memory cell

Abstract

A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional to its ML capacitance, and proportional to the current. Conventional ternary CAM cells have many matchline transistors, each contributing to the matchline capacitance. Embodiments of the present invention have a single matchline transistor between a matchline and a ground line, or tail-line, of the CAM cell. The single matchline transistor couples the matchline to the tail-line in response to a discharge signal from a compare circuit. The compare circuit can be divided into a pull-up section for driving a gate voltage level control node and a discharge section for discharging the gate voltage level control node, the discharge signal being provided at the gate voltage level control node.