The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2009

Filed:

Sep. 10, 2007
Applicants:

Takehiro Hata, Tokyo, JP;

Kazuyasu Minami, Tokyo, JP;

Inventors:

Takehiro Hata, Tokyo, JP;

Kazuyasu Minami, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/618 (2006.01); G05F 1/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is a need for preventing a MOS transistor from being destroyed due to an inrush current from an input terminal when a boost operation starts from a boost disabling state. During the boost operation, a third MOS transistor (M) turns off and a fourth MOS transistor (M) turns on to prevent a current leak from an output terminal (Vout) to an input terminal (Vin) due to a parasitic diode of a second MOS transistor (M). In the boost disabling state, the third MOS transistor turns on and the fourth MOS transistor turns off to prevent a current leak from the input terminal to the output terminal due to the parasitic diode of the second MOS transistor. When the boost operation starts from the boost disabling state, an electrode toward the output terminal of the second MOS transistor is charged before changing a substrate bias state of this transistor. In this manner, an inrush current is prevented from flowing from the input terminal to the output terminal via the parasitic diode of the second MOS transistor.


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