The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2009
Filed:
May. 02, 2008
Toshiharu Furukawa, Essex Junction, VT (US);
Mark Charles Hakey, Fairfax, VT (US);
David Vaclav Horak, Essex Junction, VT (US);
Charles William Koburger, Iii, Delmar, NY (US);
Peter H. Mitchell, Jericho, VT (US);
Toshiharu Furukawa, Essex Junction, VT (US);
Mark Charles Hakey, Fairfax, VT (US);
David Vaclav Horak, Essex Junction, VT (US);
Charles William Koburger, III, Delmar, NY (US);
Peter H. Mitchell, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.