The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2009
Filed:
Oct. 13, 2005
Rowland C. Clarke, Sykesville, MD (US);
Robert S. Howell, Silver Spring, MD (US);
Michael E. Aumer, Laurel, MD (US);
Rowland C. Clarke, Sykesville, MD (US);
Robert S. Howell, Silver Spring, MD (US);
Michael E. Aumer, Laurel, MD (US);
Northrop Grumman Systems Corporation, Los Angeles, CA (US);
Abstract
A substrate arrangement for high power semiconductor devices includes a SiC wafer having a Si layer deposited on a surface of the SiC wafer. An SOI structure having a first layer of Si, an intermediate layer of SiOand a third layer of Si, has its third layer of Si bonded to the Si deposited on the SiC wafer, forming a unitary structure. The first layer of Si and the intermediate layer of SiOof the SOI are removed, leaving a pure third layer of Si on which various semiconductor devices may be fabricated. The third layer of Si and deposited Si layer may be removed over a portion of the substrate arrangement such that one or more semiconductor devices may be fabricated on the SiC wafer while other semiconductor devices may be accommodated on the pure third layer of Si.