The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2009
Filed:
Mar. 10, 2006
Christoph Albrecht, Berkeley, CA (US);
Andreas Kuehlmann, Berkeley, CA (US);
David Seibert, Mountain View, CA (US);
Sascha Richter, Munich, DE;
Christoph Albrecht, Berkeley, CA (US);
Andreas Kuehlmann, Berkeley, CA (US);
David Seibert, Mountain View, CA (US);
Sascha Richter, Munich, DE;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
In optimizing a design of an integrated circuit, an iteration of a logic optimization process is performed that at least partially optimizes a circuit design such that there is slack remaining in one or more combinational logic paths in the circuit design following the iteration. A clock latency scheduling process is performed that respectively distributes the remaining slack of one or more respective combinational logic paths in the circuit design across respective registers in the circuit design. Another iteration of the logic optimization process is performed that uses at least a portion of the distributed slack to further optimize the circuit design.