The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2009
Filed:
Sep. 29, 2008
Yoshitaka Sasaki, Milpitas, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Tatsuya Harada, Tokyo, JP;
Nobuyuki Okuzawa, Tokyo, JP;
Satoru Sueki, Tokyo, JP;
Ryuji Hashimoto, Tokyo, JP;
Yoshitaka Sasaki, Milpitas, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Tatsuya Harada, Tokyo, JP;
Nobuyuki Okuzawa, Tokyo, JP;
Satoru Sueki, Tokyo, JP;
Ryuji Hashimoto, Tokyo, JP;
TDK Corporation, Tokyo, JP;
Headway Technologies, Inc., Milpitas, CA (US);
Abstract
A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of first-type layer portions each including a first-type semiconductor chip; and a second-type layer portion including a second-type semiconductor chip. The first-type semiconductor chip includes a plurality of memory cells. The second-type semiconductor chip includes a control circuit that controls writing and reading on and from the memory cells included in the plurality of first-type layer portions. Each layer portion includes an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each of the electrodes has an end face that is located at the side surface of the main body and connected to the wiring.