The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2009

Filed:

Jun. 28, 2004
Applicants:

Chi Nan Brian LI, Austin, TX (US);

Cheong M. Hong, Austin, TX (US);

Rana P. Singh, Austin, TX (US);

Inventors:

Chi Nan Brian Li, Austin, TX (US);

Cheong M. Hong, Austin, TX (US);

Rana P. Singh, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

Floating gates are formed in two separate polysilicon depositions steps resulting in distinct portions. The first formed portions are between isolation regions. A thick insulator is formed over the isolation regions and floating gate portions. The thick insulator is patterned to leave fences over the isolation regions. A thinning process, an isotropic etch in this example, is applied to these fences to make them thinner. Polysilicon sidewall spacers are formed on the sides of these fences. These sidewall spacers become the second portion of the floating gate. These second portions have the desired shape for significantly increasing the capacitance to the subsequently formed control gates, thereby reducing the gate voltage required for programming and erasing made by a relatively robust process.


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