The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2009

Filed:

Jun. 07, 2005
Applicants:

Philippe Meunier-beillard, Leuven, BE;

Claire Ravit, Leuven, BE;

Inventors:

Philippe Meunier-Beillard, Leuven, BE;

Claire Ravit, Leuven, BE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/80 (2006.01); H01L 31/112 (2006.01); H01L 29/792 (2006.01); H01L 31/117 (2006.01); H01L 21/8238 (2006.01); H01L 21/22 (2006.01); H01L 21/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a method of manufacturing a semiconductor strained layer and to a method of manufacturing a semiconductor device () in which a semiconductor body () of silicon is provided, at a surface thereof, with a first semiconductor layer () having a lattice of a mixed crystal of silicon and germanium and a thickness such that the lattice is substantially relaxed, and on top of the first semiconductor layer () a second semiconductor layer () is provided comprising strained silicon, in which layer () a part of the semiconductor device () is formed, and wherein measures are taken to avoid reduction of the effective thickness of the strained silicon layer () during subsequent processing needed to form the semiconductor device (), said measures comprising the use of a third layer () having a lattice of a mixed crystal of silicon and germanium. According to the invention, the third layer () is thin and positioned within the second layer () close to the interface between the first and second semiconductor layers (). In this way the resulting thickness of the strained silicon layer (), after subsequent formation of the MOSFET, can be increased, resulting in a MOSFET with better high-frequency properties. The invention also comprises a device obtained with a method according to the invention and a semiconductor substrate structure suitable for use in such a method.


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