The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2009
Filed:
Jul. 02, 2008
Vikas Agarwal, Austin, TX (US);
Michael Ju Hyeok Lee, Austin, TX (US);
Philip G. Shephard, Iii, Round Rock, TX (US);
Vikas Agarwal, Austin, TX (US);
Michael Ju Hyeok Lee, Austin, TX (US);
Philip G. Shephard, III, Round Rock, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge 'outlier' cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.