The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2009
Filed:
Nov. 15, 2005
Soroush Abbaspour, Fishkill, NY (US);
Gary S. Ditlow, Garrison, NY (US);
Chandramouli V. Kashyap, Round Rock, TX (US);
Ruchir Puri, Bladwin Place, NY (US);
Soroush Abbaspour, Fishkill, NY (US);
Gary S. Ditlow, Garrison, NY (US);
Chandramouli V. Kashyap, Round Rock, TX (US);
Ruchir Puri, Bladwin Place, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (C) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using Cas an effective load for said selected gate. Optionally, if the total gate load capacitance (C) exceeds Cby less than a minimum, the effective capacitance (C) is determined and used for determining the gate delay instead.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile