Semiconductor memory device capable of performing low-frequency test operation and method for testing the same

Abstract

A semiconductor memory device and a method for testing the same are capable of performing a low-frequency test operation even when a high-frequency external clock signal is input. The method for testing the semiconductor memory device comprises: interpreting a control command from a plurality of external control signals and generating a low-frequency operation control signal when an MRS command included in the control command designates a write and read test operation; when a write command is input as the control command, converting the write command into a low-frequency write command in response to the low-frequency operation control signal, generating an internal low-frequency clock signal in response to the low-frequency operation control signal, and performing a low-frequency write operation based on the internal low-frequency clock signal; and buffering an external clock signal to generate an internal normal-frequency clock signal and, when a read command is input as the control command, performing a read operation based on the internal normal-frequency clock signal in response to the read command.