The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2009
Filed:
Sep. 24, 2004
Hirotaka Nishizawa, Fuchu, JP;
Kenji Osawa, Hachioji, JP;
Hideo Koike, Yokohama, JP;
Junichiro Osako, Kodaira, JP;
Tamaki Wada, Higashimurayama, JP;
Hirotaka Nishizawa, Fuchu, JP;
Kenji Osawa, Hachioji, JP;
Hideo Koike, Yokohama, JP;
Junichiro Osako, Kodaira, JP;
Tamaki Wada, Higashimurayama, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A semiconductor device includes external interface terminals and processing circuits, and it is fed with an operating power source when detachably set in a host equipment. Power source feeding terminals (VCC, VSS) among the external interface terminals are long enough to keep touching the corresponding terminals of the host equipment for, at least, a predetermined time period since the separation of an extraction detecting terminal among the external interface terminals, from the corresponding terminal of the host equipment, and they are formed to be longer in the extraction direction of the semiconductor device than the extraction detecting terminal. The processing circuits include an interface control circuit () which is connected to the external interface terminals, and a rewritable nonvolatile memory () which is controlled by the interface control circuit. The nonvolatile memory stores information on the basis of the difference of the threshold voltages of memory cells. The interface control circuit causes a storage area midway of a threshold voltage initialization process to complete a process in which the threshold voltages of the memory cells are uniformalized into a predetermined threshold voltage distribution, before the power source is cut off after the separation of the extraction detecting terminal from the corresponding terminal of the host equipment.