The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2009
Filed:
Jun. 30, 2006
Jun LI, San Jose, CA (US);
Athanasius Spyrou, Sunnyvale, CA (US);
Hong Zhao, Fremont, CA (US);
Hsien-yen Chiu, Sunnyvale, CA (US);
Jun Li, San Jose, CA (US);
Athanasius Spyrou, Sunnyvale, CA (US);
Hong Zhao, Fremont, CA (US);
Hsien-Yen Chiu, Sunnyvale, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ratio of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.