The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2009
Filed:
Oct. 28, 2004
Henry Bernhardt, Dresden, DE;
Michael Stadtmüller, Dresden, DE;
Olaf Storbeck, Dresden, DE;
Stefan Kainz, Dresden, DE;
Henry Bernhardt, Dresden, DE;
Michael Stadtmüller, Dresden, DE;
Olaf Storbeck, Dresden, DE;
Stefan Kainz, Dresden, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer. The thermal nitriding is advantageously incorporated into a preanneal step for expelling oxygen from the semiconductor substrate, so that the semiconductor substrate is protected from the etching action of the expelled oxygen by the stress relief layer which is formed, there is no need for an additional temporary etching protection layer for the semiconductor substrate and the overall processing is streamlined.