The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2009

Filed:

Sep. 12, 2006
Applicants:

Oliver Desmond Patterson, Windermere, FL (US);

David M. Shuttleworth, Orlando, FL (US);

Bradley J. Albers, Dallas, TX (US);

Werner Weck, Orlando, FL (US);

Gregory Brown, Ocoee, FL (US);

Inventors:

Oliver Desmond Patterson, Windermere, FL (US);

David M. Shuttleworth, Orlando, FL (US);

Bradley J. Albers, Dallas, TX (US);

Werner Weck, Orlando, FL (US);

Gregory Brown, Ocoee, FL (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.


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