The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2009
Filed:
Dec. 06, 2006
Applicants:
Juergen Dirks, Holzkirchen, DE;
Martin Fennell, Iverheath, GB;
Iain Stickland, Eversley, GB;
Inventors:
Assignee:
LSI Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for optimizing a design of a circuit is disclosed. The method generally includes the steps of (A) identifying a plurality of first flip flops in the design and (B) replacing each of the first flip flops in a file of the design that do not have to be initialized during operations of the circuit with a respective second flip flop without an initialization capability.
Dirks, Juergen. (2009). Optimization of flip flop initialization structures with respect to design size and design closure effort from rtl to netlist (U.S. Patent No. 7546560). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7546560
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile