The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2009
Filed:
Oct. 21, 2005
Sharon Levin, Haifa, IL;
Shye Shapira, Haifa, IL;
Ira Naot, Zikhron Yaakov, IL;
Robert J. Strain, San Jose, CA (US);
Yossi Netzer, Hadera, IL;
Sharon Levin, Haifa, IL;
Shye Shapira, Haifa, IL;
Ira Naot, Zikhron Yaakov, IL;
Robert J. Strain, San Jose, CA (US);
Yossi Netzer, Hadera, IL;
Tower Semiconductor Ltd., Migdal Haemek, IL;
Abstract
A Schottky diode exhibiting low series resistance is efficiently fabricated using a substantially standard CMOS process flow by forming the Schottky diode using substantially the same structures and processes that are used to form a field effect transistor (FET) of a CMOS IC device. Polycrystalline silicon, which is used to form the gate structure of the FET, is utilized to form an isolation structure between the Schottky barrier and backside structure of the Schottky diode. Silicide (e.g., cobalt silicide (CoSi)) structures, which are utilized to form source and drain metal-to-silicon contacts in the FET, are used to form the Schottky barrier and backside Ohmic contact of the Schottky diode. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.