The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2009
Filed:
Dec. 06, 2005
Zhigang Wang, Sewickley, PA (US);
Elias Fallon, Pittsburgh, PA (US);
Regis R. Colwell, Gibsonia, PA (US);
Zhigang Wang, Sewickley, PA (US);
Elias Fallon, Pittsburgh, PA (US);
Regis R. Colwell, Gibsonia, PA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of the array in the memory of the computer with a corresponding layout instance of the circuit device, wherein each layout instance represents a physical arrangement of material(s) that form the corresponding selected circuit device.