The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2009
Filed:
Feb. 27, 2004
Gerry Ashton, Castleton, VT (US);
Kevin A. Duncan, Milton, VT (US);
Terry D. Keim, Williston, VT (US);
Toshiharu Saitoh, South Burlington, VT (US);
Tad J. Wilder, South Hero, VT (US);
Gerry Ashton, Castleton, VT (US);
Kevin A. Duncan, Milton, VT (US);
Terry D. Keim, Williston, VT (US);
Toshiharu Saitoh, South Burlington, VT (US);
Tad J. Wilder, South Hero, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A shift register latch (SRL) () compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree (). The SRL includes a master latch (), a slave latch () and a circuit element () connected between the scan clock tree and the master latch. The scan clock generates a clock signal () having regularly spaced pulses during the scan phase of the LSSD testing. The circuit element generates a short-pulsed signal (') based on the scan clock signal for triggering the master latch. This short-pulsed signal compensates for any delay in the clock signal due to the physical length of the signal path from the scan clock to the SRL, thereby preventing scanned data from being flushed through a scan chain of the SRLs of the present invention