The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2009
Filed:
Dec. 05, 2005
Howard Tang, San Jose, CA (US);
Jack T. Wong, Fremont, CA (US);
Clark Wilkinson, Austin, TX (US);
Jeffrey S. Byrne, Portland, OR (US);
Howard Tang, San Jose, CA (US);
Jack T. Wong, Fremont, CA (US);
Clark Wilkinson, Austin, TX (US);
Jeffrey S. Byrne, Portland, OR (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks having boundary scan cells that are adapted to precondition registers within a logic area of the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.