The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2009

Filed:

Sep. 18, 2006
Applicants:

Takashi Onishi, Kobe, JP;

Masao Mizuno, Kobe, JP;

Mikako Takeda, Kobe, JP;

Susumu Tsukimoto, Kyoto, JP;

Tatsuya Kabe, Sakyo-ku, JP;

Toshifumi Morita, Sakyo-ku, JP;

Miki Moriyama, Sakyo-ku, JP;

Kazuhiro Ito, Sakyo-ku, JP;

Masanori Murakami, Sakyo-ku, JP;

Inventors:

Takashi Onishi, Kobe, JP;

Masao Mizuno, Kobe, JP;

Mikako Takeda, Kobe, JP;

Susumu Tsukimoto, Kyoto, JP;

Tatsuya Kabe, Sakyo-ku, JP;

Toshifumi Morita, Sakyo-ku, JP;

Miki Moriyama, Sakyo-ku, JP;

Kazuhiro Ito, Sakyo-ku, JP;

Masanori Murakami, Sakyo-ku, JP;

Assignee:

Kobe Steel, Ltd., Kobe-shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.


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