The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2009

Filed:

Mar. 18, 2005
Applicants:

Dun-nian Yaung, Taipei, TW;

Sou-kuo Wu, Hsinchu, TW;

Ho-ching Chen, Hsinchu, TW;

Inventors:

Dun-Nian Yaung, Taipei, TW;

Sou-Kuo Wu, Hsinchu, TW;

Ho-Ching Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/8244 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a salicided MOS and a one-sided salicided MOS device on a semiconductor substrate. A conformal oxide layer and an organic layer are sequentially formed on first and second MOS devices and the substrate. The first MOS has a first gate structure, a first spacer and first and second doped regions. The second MOS has a second gate structure, a second spacer and third and fourth doped regions. Anisotropic etching is performed to remove part of the organic layer until the oxide layer on the first and the second gate structures is exposed, wherein a remaining organic layer is left above the substrate. The oxide layer on the first and the second gate structures is removed. The remaining organic layer is removed. The oxide layer on the first, second, and third doped regions is removed. Thus, a silicide layer cannot form on the fourth doped region.


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