The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2009
Filed:
Aug. 11, 2006
Bart Reynolds, Seattle, WA (US);
Keith R. Bean, Greeley, CO (US);
Daniel P. Kirkwood, Denver, CO (US);
James F. Barei, Seattle, WA (US);
Benjamin D. Ralston, Bellevue, WA (US);
Bart Reynolds, Seattle, WA (US);
Keith R. Bean, Greeley, CO (US);
Daniel P. Kirkwood, Denver, CO (US);
James F. Barei, Seattle, WA (US);
Benjamin D. Ralston, Bellevue, WA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A processor-implemented method is provided for determining networks of a tile module of a programmable logic device (PLD) design. A netlist describing the PLD design and a tile module identification are input. Characterization data is input for a sub-module of the tile module that specifies modeled pins of the sub-module, which is either a switchbox or a logic site. Connectivity pins of the tile module are determined. Each connectivity pin of one of the tile instances is connected in the netlist to a modeled pin of an instance of the sub-module within a tile instance. Networks of the tile module are determined that connect a first subset of the connectivity pins of the tile module and a second subset of the modeled pins of an instance of the sub-module within the tile module. A specification is output for each of the networks including the first subset and the second subset.