The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2009
Filed:
Dec. 08, 2006
Jui-jen Wu, Hsinchu, TW;
Kun-lung Chen, Taipei, TW;
Hung-jen Liao, Hsin-Chu, TW;
Yung-lung Lin, Taichung, TW;
Chen Yen-huei, Hsinchu, TW;
Dao-ping Wang, Hsinchu, TW;
Jui-Jen Wu, Hsinchu, TW;
Kun-Lung Chen, Taipei, TW;
Hung-Jen Liao, Hsin-Chu, TW;
Yung-Lung Lin, Taichung, TW;
Chen Yen-Huei, Hsinchu, TW;
Dao-Ping Wang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.