The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2009

Filed:

Sep. 07, 2007
Applicants:

Chikayoshi Morishima, Tokyo, JP;

Tokuya Osawa, Tokyo, JP;

Masaru Haraguchi, Tokyo, JP;

Yoshihiro Yamashita, Itami, JP;

Inventors:

Chikayoshi Morishima, Tokyo, JP;

Tokuya Osawa, Tokyo, JP;

Masaru Haraguchi, Tokyo, JP;

Yoshihiro Yamashita, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H03K 19/003 (2006.01); H03K 19/094 (2006.01); H03K 19/0175 (2006.01); H03K 19/084 (2006.01); G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing the output buffer circuit which are equal in size are measured. An impedance code generating circuit outputs impedance codes corresponding to the impedance values of the reference transistors to an output buffer code generating circuit based on the result of the measurement from the impedance measuring circuit. The output buffer code generating circuit generates output buffer codes for adjusting the impedance of the output buffer circuit by performing an arithmetic operation process to provide an objective impedance based on the impedance codes.


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