The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2009
Filed:
Jun. 09, 2006
Jae-kyu Ha, Suwon-si, KR;
Jun Seo, Suwon-si, KR;
Min-chul Chae, Suwon-si, KR;
Yong-sun Ko, Suwon-si, KR;
Young-mi Lee, Yongin-si, KR;
Jae-seung Hwang, Suwon-si, KR;
Jae-Kyu Ha, Suwon-si, KR;
Jun Seo, Suwon-si, KR;
Min-Chul Chae, Suwon-si, KR;
Yong-Sun Ko, Suwon-si, KR;
Young-Mi Lee, Yongin-si, KR;
Jae-Seung Hwang, Suwon-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.