The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2009
Filed:
Feb. 29, 2008
Bruno Ghyselen, Seyssinet, FR;
Daniel Bensahel, Grenoble, FR;
Thomas Skotnicki, Crolles-Montfort, FR;
Bruno Ghyselen, Seyssinet, FR;
Daniel Bensahel, Grenoble, FR;
Thomas Skotnicki, Crolles-Montfort, FR;
S.O.I. Tec Silicon on Insulator Technologies, Bernin, FR;
Abstract
A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness. A first wafer having a strained layer of a semiconductor material on a matching layer is provided, with the semiconductor material having a first lattice parameter corresponding to a relaxed state and a first critical thickness corresponding to the first strained state, and the first thickness is less than the first critical thickness, The matching layer has a matching lattice parameter that is sufficiently different than the first lattice parameter to retain the strained layer in the strained state, The strained layer is transferred to a receiving substrate selected to provide the transferred strained layer with a second critical thickness that is greater than the first critical thickness, and additional semiconductor material is grown on the transferred strained layer to provide a second thickness that is greater than the first critical thickness and less than the second critical thickness, The invention also relates to the semiconductor structures that can be produced by the process.