The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2009
Filed:
Feb. 13, 2006
Suresh Marisetty, Fremont, CA (US);
Baskaran Ganesan, Bangalore, IN;
Gautam Bhagwandas Doshi, Bangalore, IN;
Murugasamy Nachimuthu, Hillsboro, OR (US);
Koichi Yamada, Los Gatos, CA (US);
Jose A. Vargas, Rescue, CA (US);
Jim Crossland, Banks, OR (US);
Stan J. Domen, Roseville, CA (US);
Suresh Marisetty, Fremont, CA (US);
Baskaran Ganesan, Bangalore, IN;
Gautam Bhagwandas Doshi, Bangalore, IN;
Murugasamy Nachimuthu, Hillsboro, OR (US);
Koichi Yamada, Los Gatos, CA (US);
Jose A. Vargas, Rescue, CA (US);
Jim Crossland, Banks, OR (US);
Stan J. Domen, Roseville, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.