The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2009
Filed:
Oct. 19, 2006
Zhibo Zhang, Plano, TX (US);
Cloves Rinn Cleavelin, Dallas, TX (US);
Michael Francis Pas, Richardson, TX (US);
Stephanie Watts Butler, Richardson, TX (US);
Mike Watson Goodwin, Murphy, TX (US);
Satyavolu Srinivas Papa Rao, Garland, TX (US);
Zhibo Zhang, Plano, TX (US);
Cloves Rinn Cleavelin, Dallas, TX (US);
Michael Francis Pas, Richardson, TX (US);
Stephanie Watts Butler, Richardson, TX (US);
Mike Watson Goodwin, Murphy, TX (US);
Satyavolu Srinivas Papa Rao, Garland, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.