The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
Apr. 04, 2008
Malede Wondmagegne Berhanu, Colchester, VT (US);
Christopher Douglas Hanudel, Williston, VT (US);
Mark William Kuemerle, Essex Junction, VT (US);
David Wills Milton, Underhill, VT (US);
Clarence Rosser Ogilvie, Huntington, VT (US);
Jack Robert Smith, South Burlington, VT (US);
Malede Wondmagegne Berhanu, Colchester, VT (US);
Christopher Douglas Hanudel, Williston, VT (US);
Mark William Kuemerle, Essex Junction, VT (US);
David Wills Milton, Underhill, VT (US);
Clarence Rosser Ogilvie, Huntington, VT (US);
Jack Robert Smith, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a predetermined section of a data window. Additionally, the logic block monitors a clock signal along predetermined portions of the delay line to identify the predetermined section of the data window. Once the predetermined section of the data window is identified the logic block forwards the data associated with the predetermined section to an output pin, with the proviso that no memory element is present, and with the proviso that no feedback line is present.