The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
Jun. 28, 2005
Patrice M. Parris, Phoenix, AZ (US);
Weize Chen, Phoenix, AZ (US);
John M. Mckenna, Chandler, AZ (US);
Jennifer H. Morrison, Chandler, AZ (US);
Moaniss Zitouni, Gilbert, AZ (US);
Richard J. DE Souza, Tempe, AZ (US);
Patrice M. Parris, Phoenix, AZ (US);
Weize Chen, Phoenix, AZ (US);
John M. McKenna, Chandler, AZ (US);
Jennifer H. Morrison, Chandler, AZ (US);
Moaniss Zitouni, Gilbert, AZ (US);
Richard J. De Souza, Tempe, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A tunable antifuse element () and method of fabricating the tunable antifuse element, including a substrate material () having an active area () formed in a surface, a gate electrode () having at least a portion positioned above the active area (), and a dielectric layer () disposed between the gate electrode () and the active area (). The dielectric layer () including the fabrication of one of a tunable stepped structure (). During operation, a voltage applied between the gate electrode () and the active area () creates a current path through the dielectric layer () and a rupture of the dielectric layer () in a plurality of rupture regions (). The dielectric layer () is tunable by varying the stepped layer thicknesses and the geometry of the layer.