The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2009
Filed:
Jun. 19, 2006
Jeong-duk Sohn, Pleasanton, CA (US);
Jeong-Duk Sohn, Pleasanton, CA (US);
ZMOS Technology, Inc., San Jose, CA (US);
Abstract
An SRAM circuit structure and method for reducing leakage currents and/or increasing the speed of the devices. Various forms of SRAM devices may be fabricated utilizing the techniques, such as single port and dual port RAM devices. By way of example the SRAM structure utilizes separate write and read lines, splits the circuit into portions which can benefit from having differing threshold levels, and can allow splitting read path transistors for connection to a first terminal and a virtual node connected to a source transistor. The structure is particularly well suited for forming transistors in a combination of NMOS and PMOS, or solely in NMOS. Memory arrays may be organized according to the invention in a number of different distributed or lumped arrangements with the reference read paths and sense blocks being either shared or dedicated.