The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2009
Filed:
Mar. 06, 2008
Prabha Jairam, Fremont, CA (US);
Himanshu J. Verma, Mountain View, CA (US);
Prabha Jairam, Fremont, CA (US);
Himanshu J. Verma, Mountain View, CA (US);
XILINX, Inc., San Jose, CA (US);
Abstract
A test circuit in an integrated circuit (or) is used for verifying a critical path of a circuit () under test. The test circuit can include a sequence generator () generating a data signal for the critical path, a source sequential circuit () for receiving the data signal coupled to an input of the critical path, a destination sequential circuit (or) for receiving an output of the critical path, and an analyzer circuit (or) for verification of timing of the critical path by measuring timing from the source sequential circuit to a clock enable pin () or a set/reset pin () of the destination sequential circuit. The test circuit can further include a controller circuit () for strobing a comparison circuit () in the analyzer circuit at a predetermined clock time. The integrated circuit can be part of an FPGA or FPGA fabric.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile