The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2009

Filed:

Jul. 13, 2006
Applicants:

Hyang-ja Yang, Suwon-si, KR;

Su-jin Park, Seoul, KR;

Uk-rae Cho, Suwon-si, KR;

Sung-hoon Kim, Seongnam-si, KR;

Inventors:

Hyang-Ja Yang, Suwon-si, KR;

Su-Jin Park, Seoul, KR;

Uk-Rae Cho, Suwon-si, KR;

Sung-Hoon Kim, Seongnam-si, KR;

Assignee:

Samsung Electronics, Ltd, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench isolation, and a second group of MOS transistors having second drain regions and second source regions allocated to the group active region. The second group is disposed between the first group and an edge of the group active region. One or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode.


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