The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2009

Filed:

Aug. 18, 2006
Applicants:

Hemangi Umakant Gajjewar, Santa Clara, CA (US);

Ingming Chang, San Jose, CA (US);

Jungtae Kwon, San Jose, CA (US);

Cezary Pietrzyk, Los Gatos, CA (US);

Moon-hae Son, San Jose, CA (US);

Inventors:

Hemangi Umakant Gajjewar, Santa Clara, CA (US);

Ingming Chang, San Jose, CA (US);

Jungtae Kwon, San Jose, CA (US);

Cezary Pietrzyk, Los Gatos, CA (US);

Moon-Hae Son, San Jose, CA (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system, method and computer program product are provided for producing an instance of a memory device from a banked memory architecture. The banked memory architecture specifies a maximum number of memory banks and a maximum number of rows per memory bank. The method comprises the step of receiving input parameters indicating a number of properties of the memory device, the properties comprising at least a number of rows R for the memory device. Thereafter, a degeneration process is performed on the banked memory architecture in order to produce the instance of a memory device having those properties. The degeneration process comprises the steps of: (i) selecting a number of memory banks B for the instance, where the number is an integer less than or equal to the maximum number of memory banks specified by the banked memory architecture, and B is not constrained to be a factor of R; and (ii) partitioning the number of rows R amongst the selected memory banks such that in each memory bank the number of rows in that memory bank is an integer less than or equal to the maximum number of rows per memory bank specified by the banked memory architecture. This has been found to provide a very flexible technique for producing instances from a banked memory architecture allowing fine granularity in the number of rows provided, which is particularly suitable for highly banked memory architectures.


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