The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2009
Filed:
Oct. 07, 2005
Kerry Bernstein, Underhill, VT (US);
Paul Coteus, Yorktown, NY (US);
Ibrahim M. Elfadel, Ossining, NY (US);
Philip Emma, Danbury, CT (US);
Daniel J. Friedman, Sleepy Hollow, NY (US);
Ruchir Puri, Baldwin Place, NY (US);
Mark B. Ritter, Sherman, CT (US);
Jeannine Trewhella, Peekskill, NY (US);
Albert M. Young, Fishkill, NY (US);
Kerry Bernstein, Underhill, VT (US);
Paul Coteus, Yorktown, NY (US);
Ibrahim M. Elfadel, Ossining, NY (US);
Philip Emma, Danbury, CT (US);
Daniel J. Friedman, Sleepy Hollow, NY (US);
Ruchir Puri, Baldwin Place, NY (US);
Mark B. Ritter, Sherman, CT (US);
Jeannine Trewhella, Peekskill, NY (US);
Albert M. Young, Fishkill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.