The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2009
Filed:
Aug. 02, 2005
Hirotoshi Kubo, Osaka, JP;
Masanao Kitagawa, Osaka, JP;
Masahito Onda, Osaka, JP;
Hiroaki Saito, Osaka, JP;
Eiichiroh Kuwako, Osaka, JP;
Hirotoshi Kubo, Osaka, JP;
Masanao Kitagawa, Osaka, JP;
Masahito Onda, Osaka, JP;
Hiroaki Saito, Osaka, JP;
Eiichiroh Kuwako, Osaka, JP;
Sanyo Electric Co., Ltd, Moriguchi-chi, Osaka, unknown;
Abstract
A power MOSFET comprises: a semiconductor substrateof a first conduction type; a drain layerof the first conduction type and formed on a surface layer of the substrate; a gate insulating filmformed in a partial region on the drain layer; a gate electrodeformed on the gate insulating film; an insulating filmformed on the gate electrode; a side wall insulatorformed on side walls of the gate insulating film, the gate electrode, and the insulating film; a recess formed on the drain layerand in a region other than a region where the gate electrodeand the side wall insulatorare formed; a channel layerof a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrodeis formed; a source region layerof the one conduction type and formed on the channel layeroutside the recess; and a wiring layerformed to cover the channel layerwhich is exposed through the recess, the side wall insulator, and the insulating film.