The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2009
Filed:
Jun. 01, 2005
Cha-hsin Lin, Hsinchu, TW;
Zing-way Pei, Hsinchu, TW;
Ming-jinn Tsai, Hsinchu, TW;
Shing-chii LU, Hsinchu, TW;
Cha-Hsin Lin, Hsinchu, TW;
Zing-Way Pei, Hsinchu, TW;
Ming-Jinn Tsai, Hsinchu, TW;
Shing-Chii Lu, Hsinchu, TW;
Industrial Technology Research Institute, Hsinchu, TW;
Abstract
A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.