The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2009
Filed:
Jun. 28, 2004
Hiroshi Noro, Ibaraki, JP;
Koji Akazawa, Ibaraki, JP;
Masayuki Yamamoto, Ibaraki, JP;
Yasuhiko Yamamoto, Ibaraki, JP;
Hiroshi Noro, Ibaraki, JP;
Koji Akazawa, Ibaraki, JP;
Masayuki Yamamoto, Ibaraki, JP;
Yasuhiko Yamamoto, Ibaraki, JP;
Nitto Denko Corporation, Ibaraki-shi, JP;
Abstract
A laminated sheet for adhering to a circuit side of a projected electrode-mounting wafer in a step of grinding a backside of the wafer, wherein the laminated sheet comprises at least a layer (layer A) contacting with the circuit side, made of a thermosetting resin, a layer (layer B) directly laminated on the layer A, made of a thermoplastic resin having a tensile modulus of from 1 to 300 MPa at 40° to 80° C., and an outermost layer (layer C) made of a thermoplastic resin which is non-plastic at a temperature of at least 25° C.; A method for manufacturing a semiconductor device, comprising the steps of grinding a backside of a projected electrode-mounting wafer wherein the laminated sheet is adhered to a circuit side of the wafer, removing other layers besides the layer A of the laminated sheet, and cutting the wafer into individual chips; and a semiconductor device obtainable by the method.