The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2009

Filed:

Jun. 25, 2007
Applicants:

Venu M. Kondapalli, Sunnyvale, CA (US);

Wei Guang LU, San Jose, CA (US);

P. Hugo Lamarche, Campbell, CA (US);

Inventors:

Venu M. Kondapalli, Sunnyvale, CA (US);

Wei Guang Lu, San Jose, CA (US);

P. Hugo Lamarche, Campbell, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); H03K 19/173 (2006.01); H03K 17/693 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus is provided to implement rapid reconfiguration during either a full, or partial, reconfiguration of a programmable logic device (PLD). Rapid reconfiguration is facilitated by a massively parallel configuration data bus that is created to simultaneously reconfigure the entire height of a reconfiguration memory space. A direct link may be provided to the configuration memory space of the PLD by utilizing interconnect and input/output resources to form the massively parallel configuration data bus. An indirect link may also be provided to the entire configuration memory space by utilizing existing random access memory (RAM) resources within the PLD as configuration bitstream buffers.


Find Patent Forward Citations

Loading…