The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2009
Filed:
Sep. 14, 2007
Applicants:
Jin Yuan Lee, Hsinchu, TW;
Mou-shiung Lin, Hsinchu, TW;
Inventors:
Jin Yuan Lee, Hsinchu, TW;
Mou-Shiung Lin, Hsinchu, TW;
Assignee:
Megica Corporation, Hsin-Chu, TW;
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.
Lee, Jin. (2009). Structure of high performance combo chip and processing method (U.S. Patent No. 7517778). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7517778
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile