The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2009

Filed:

Nov. 30, 2005
Applicants:

Philip V. Kaszuba, Essex Junction, VT (US);

Theodore M. Levin, Burlington, VT (US);

David P. Vallett, Fairfax, VT (US);

Inventors:

Philip V. Kaszuba, Essex Junction, VT (US);

Theodore M. Levin, Burlington, VT (US);

David P. Vallett, Fairfax, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01H 31/02 (2006.01); G01R 27/08 (2006.01); G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material.


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