The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2009
Filed:
Aug. 19, 2005
Ming-huan Tsai, Hsinchu, TW;
Fang-cheng Chen, Hsin-Chu, TW;
Chao-cheng Chen, Shin-Chu County, TW;
Syun-ming Jang, Hsin-Chu, TW;
Ming-Huan Tsai, Hsinchu, TW;
Fang-Cheng Chen, Hsin-Chu, TW;
Chao-Cheng Chen, Shin-Chu County, TW;
Syun-Ming Jang, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.