The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2009

Filed:

May. 09, 2005
Applicants:

Mark A. Anders, Hillsboro, OR (US);

Sanu K. Mathew, Hillsboro, OR (US);

Nanda Siddaiah, Portland, OR (US);

Sapumal Wijeratne, Portland, OR (US);

Inventors:

Mark A. Anders, Hillsboro, OR (US);

Sanu K. Mathew, Hillsboro, OR (US);

Nanda Siddaiah, Portland, OR (US);

Sapumal Wijeratne, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.


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