Semiconductor memory device with mos transistors each having floating gate and control gate

Abstract

A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m<n). The second address decode circuit decodes (n−m) bits in the row address signal. The transfer gate supplies the output of the first address decode circuit to the word line according to the output of the second address decoded circuit.