Circuit and method for an sram with two phase word line pulse

Abstract

A circuit and method for providing a two phase word line pulse for use during access cycles in an SRAM memory with improved operating margins. A first and a second timing circuit are provided and a word line voltage suppression circuit is provided to reduce the voltage on the active word lines in a first phase of a word line pulse, and to allow the word lines to rise to a second, unsuppressed voltage in a second phase of the word line pulse, responsive to the first and second timing circuits. The first and second timing circuits observe the bit lines voltage discharge and provide control signals active when the bit lines are discharged past certain thresholds, these signals control the voltage suppression circuit. Operating margins for the SRAM are therefore improved. Methods for operating an SRAM using a two phase word line pulse are provided.